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STK12C68-M
STK12C68-M
CMOS nvSRAM 8K x 8 AutoStoreTM Nonvolatile Static RAM MIL-STD-883 / SMD # 5962-94599
FEATURES * 40, 45 and 55ns Access Times * 15 mA ICC at 200ns Access Speed * Automatic STORE to EEPROM on Power Down * Hardware or Software initiated STORE to
EEPROM
DESCRIPTION The Simtek STK12C68-M is a fast static RAM (40, 45 and 55ns), with a nonvolatile EEPROM element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) take place automatically upon power down using charge stored in an external 100 F capacitor. Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on power up. Software sequences may also be used to initiate both STORE and RECALL operations. A STORE can also be initiated via a single pin. The STK12C68-M is available in the following packages: a 28-pin 300 mil ceramic DIP and 28-pad LCC.
* Automatic STORE Timing * 100,000 STORE cycles to EEPROM * 10 year data retention in EEPROM * Automatic RECALL on Power Up * Software initiated RECALL from EEPROM * Unlimited RECALL cycles from EEPROM * Single 5V10% Operation * Available in multiple standard packages
LOGIC BLOCK DIAGRAM
EEPROM ARRAY 256 x 256 A3 A4
ROW DECODER
PIN CONFIGURATIONS
VCAP VCCX
VCAP A 12 A7
HSB A8 A9 A11 G A 10 E DQ 7 DQ 6
W
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCCX W HSB A8 A9 A 11 G A 10 E DQ 7 DQ 6 DQ 5 DQ 4 DQ 3
A7 A 12
3 2
STORE STATIC RAM ARRAY 256 x 256
A0 A 12
A6 A5 A4 A3 A2 A1 A0 DQ 0 DQ 1
4 5 6 7 8 9 10 11 12
1
28 27 26 25 24 23
A6 A5 A4 A3 A2 A1 A0 DQ 0 DQ 1 DQ 2 VSS
A5 A6 A7 A8 A9 A12
DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
RECALL
TOP VIEW
22 21 20 19 18
STORE/ RECALL CONTROL
HSB
13 14 15 16 17
DQ2
DQ3
DQ4
DQ5
Vss
28 - LCC
COLUMN I/O
INPUT BUFFERS
28 - 300 C-DIP
PIN NAMES
A0 - A12 W DQ0 - DQ7 E
G
COLUMN DECODER
Address Inputs Write Enable Data In/Out Chip Enable Output Enable Power (+5V) Ground Capacitor Hardware Store/Busy
A0
A1
A2
A10
A 11
G VCCX VSS
E W
VCAP HSB
4-53
STK12C68-M ABSOLUTE MAXIMUM RATINGSa
Voltage on typical input relative to VSS. . . . . . . . . . . . . -0.6V to 7.0V Voltage on DQ0-7 and G. . . . . . . . . . . . . . . . . . .-0.5V to (VCC+0.5V) Temperature under bias . . . . . . . . . . . . . . . . . . . . . . -55C to 125C Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA
(One output at a time, one second duration)
Note a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC CHARACTERISTICS
SYMBOL ICC b
1
(VCC = 5.0V 10%)d
MIN MAX 85 80 75 UNITS mA mA mA mA tAVAV = 40ns tAVAV = 45ns tAVAV = 55ns All inputs 0.2V or (VCC - 0.2V) E 0.2V, W (VCC - 0.2V) others 0.2V or (VCC - 0.2V) 4 mA All inputs 0.2V or (VCC - 0.2V) tAVAV = 40ns tAVAV = 45ns tAVAV = 55ns E VIH; all others cycling E (VCC - 0.2V) VCC = max VIN = V SS to VCC VCC = max VOUT = VSS to VCC All Inputs All Inputs IOUT = -4mA except HSB IOUT = 8mA except HSB NOTES
PARAMETER Average VCC Current
ICC
2
Average VCC Current During STORE Average VCC Current at tAVAV = 200ns Average VCC current during AutoStoreTM cycle
8
ICC b
3
15
mA
ICC
4
ISB c
1
Average VCC Current (Standby, Cycling TTL Input Levels)
35 32 28
mA mA mA
ICC b
2
Average VCC Current (Standby, Stable CMOS Input Levels) Input Leakage Current (Any Input)
4 1 5
mA A A
IILK IOLK VIH VIL VOH VOL TA
Off State Output Leakage Current
Input Logic "1" Voltage Input Logic "0" Voltage Output Logic "1" Voltage Output Logic "0" Voltage Operating Temperature
2.2 VSS-.5 2.4
VCC+.5 0.8
V V V
0.4 -55 125
V C
Note b: ICC and ICC are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. 1 3 Note c: Bringing E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. Note d: VCC reference levels throughout this datasheet refer to VCCX if that is where the power supply connection is made, or VCAP if VCCX is connected to ground.
AC TEST CONDITIONS
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to 3V Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . 5ns Input and Output Timing Reference Levels. . . . . . . . . . . . . . 1.5V Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
Output 5.0V
480 Ohms
CAPACITANCE (TA=25C, f=1.0MHz)
SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance MAX 8 7 UNITS pF pF CONDITIONS V = 0 to 3V V = 0 to 3V
255 Ohms
30pF INCLUDING SCOPE AND FIXTURE
Figure 1: AC Output Loading
4-54
STK12C68-M
SRAM MEMORY OPERATION
READ CYCLES #1 & #2
SYMBOLS NO. 1 2 3 4 5 6 7 8 9 10 11 #1, #2 tELQV tAVAV tAVQVg tGLQV tAXQX tELQX tEHQZh tGLQX tGHQZ h tELICCHe tEHICCLc,e Alt. tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS PARAMETER Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby 0 35 0 17 0 45 5 5 17 0 20 0 55 40 40 20 5 5 20 0 25 STK12C68-40M MIN MAX 40 45 45 25 5 5 25 STK12C68-45M MIN MAX 45 55 55 35
(VCC = 5.0V 10%)d
STK12C68-55M MIN MAX 55 UNITS ns ns ns ns ns ns ns ns ns ns ns
Note c: Bringing E VIH will not produce standby currents until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. Note e: Parameter guaranteed but not tested. Note f: For READ CYCLE #1 and #2, W is high for entire cycle. Note g: Device is continuously selected with E low and G low. Note h: Measured 200mV from steady state output voltage.
READ CYCLE #1 f,g
2 tAVAV ADDRESS 5 tAXQX DQ (Data Out) 3 tAVQV
DATA VALID
READ CYCLE #2 f
2 tAVAV ADDRESS 1 tELQV 11 tEHICCL 7 tEHQZ 9 tGHQZ
DATA VALID
E
tELQX 4 tGLQV 8 tGLQX
6
G
DQ (Data Out) tELICCH ACTIVE ICC STANDBY 10
4-55
STK12C68-M WRITE CYCLES #1 & #2
SYMBOLS NO. 12 13 14 15 16 17 18 19 20 21 #1 tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX tWLQZ h,j tWHQX #2 tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX Alt. tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW PARAMETER Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold After End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active After End of Write 5 STK12C68-40M MIN 35 30 30 18 0 30 0 0 17 5 MAX STK12C68-45M MIN 45 35 35 20 0 35 0 0 20 5 MAX
(VCC = 5.0V 10%)d
STK12C68-55M MIN 55 45 45 25 0 45 0 0 25 MAX UNITS ns ns ns ns ns ns ns ns ns ns
Note h: Measured 200mV from steady state output voltage. Note i: Note j: E or W must be VIH during address transitions. If W is low when E goes low, the outputs remain in the high impedance state.
WRITE CYCLE #1: W CONTROLLED i
12 tAVAV ADDRESS 14 tELWH E 18 tAVWL W 17 tAVWH 19 tWHAX
13 tWLWH 15 tDVWH 16 tWHDX
DATA IN tWLQZ DATA OUT
PREVIOUS DATA
DATA VALID
20
21 tWHQX
HIGH IMPEDANCE
WRITE CYCLE #2: E CONTROLLED i
12 tAVAV ADDRESS 18 tAVEL E 17 tAVEH W 13 tWLEH 15 tDVEH DATA IN
DATA VALID
14 tELEH
19 tEHAX
16 tEHDX
DATA OUT
HIGH IMPEDANCE
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STK12C68-M
NONVOLATILE MEMORY OPERATION
MODE SELECTION
E H L L L W X H L H HSB H H H H A12 - A0(hex) X X X 0000 1555 0AAA 1FFF 10F0 0F0F L H H 0000 1555 0AAA 1FFF 10F0 0F0E X X L X MODE Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL I/O Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z Output High Z ICC2/Standby Active POWER Standby Active Active Active k,l k,l k,l k,l k,l k k,l k,l k,l k,l k,l k m l NOTES
STORE/Inhibit
Note k: The six consecutive addresses must be in order listed - (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and diagrams for further details. Note l: I/O state assumes that G VIL. Activation of nonvolatile cycles does not depend on the state of G. Note m: HSB initiated STORE operation actually occurs only if a WRITE has been done since last STORE operation. After the STORE (if any) completes, the part will go into standby mode inhibiting all operation until HSB rises.
HARDWARE STORE /RECALL
SYMBOLS NO. 22 23 24 25 26 tRECALL tSTORE tDELAY tRECOVER tASSERT VSWITCH IHSB_OL IHSB_OH Note e: Note n: Note o: tHLHH tHLQZ tHHQX tHLHX PARAMETER MIN MAX 20 10 1 300 250 4.0 3 5 60 4.5 UNITS s ms s ns ns V mA A HSB = VOL, Note e, n HSB = VIL, Note e, n Note e Note e NOTES Note o VCC 4.5V
RECALL Cycle Duration STORE Cycle Duration
HSB Low to Inhibit On HSB High to Inhibit Off External STORE Pulse Width Low Voltage Trigger Level HSB Output Low Current HSB Output High Current
These parameters guaranteed but not tested. HSB is an I/O that has a weak internal pullup; it is basically an open drain output. It is meant to allow up to 32 STK12C68-Ms to be ganged together for simultaneous storing. Do not use HSB to pullup any external circuitry other than other STK12C68-M HSB pins. A RECALL cycle is initiated automatically at power up when VCC exceeds VSWITCH. tRECALL is measured from the point at which VCC exceeds 4.5V.
HARDWARE STORE /RECALL
VSWITCH VCAP 26 tASSERT 24 tDELAY
HSB W
22 tRECALL
24 tDELAY
25 tRECOVER
RECALL STORE SRAM Inhibit
Power Up RECALL Brown Out RECALL 23 tSTORE 23 tSTORE 23 tSTORE
Power Down STORE
HSB Initiated STORE
Software STORE
4-57
STK12C68-M SOFTWARE STORE/RECALL CYCLE
SYMBOLS NO. 28 29 30 31 32 Std. tAVAV tELQZp tAVELN tELEHNq,r tEHAXN tAE tEP tEA Alt. tRC PARAMETER STK12C68-40M MIN 35 85 0 25 0 0 35 0 MAX STK12C68-45M MIN 45 85 0 45 0 MAX
(VCC = 5.0V 10%)d
STK12C68-55M MIN 55 85 MAX UNITS ns ns ns ns ns
STORE/RECALL Initiation Cycle Time
Chip Enable to Output Inactive Address Set-up to Chip Enable Chip Enable Pulse Width Chip Disable to Address Change
Note p: Once the software STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs. Note q: Noise on the E pin may trigger multiple read cycles from the same address and abort the address sequence. Note r: If the Chip Enable Pulse Width is less than tELQV (see READ CYCLE #2) but greater than or equal to tELEHN, then the data may not be valid at the end of the low pulse, however the STORE or RECALL will still be initiated. Note s: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW throughout. Addresses #1 through #6 are found in the MODE SELECTION table. Address #6 determines whether the STK12C68-M performs a STORE or RECALL. Note t: E must be used to clock in the address sequence for the Software STORE and RECALL cycles.
SOFTWARE STORE/RECALL CYCLE q,r,t
28 tAVAV ADDRESS tAVELN E 23 tSTORE 29 tELQZ DQ(Data Out)
VALID VALID HIGH IMPEDANCE ADDRESS #1
28 tAVAV
ADDRESS #2 ADDRESS #6
30
tELEHN
31
tEHAXN
32
22 tRECALL
4-58
STK12C68-M
DEVICE OPERATION
The STK12C68-M has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as a standard fast static RAM. In nonvolatile mode, data is transferred from SRAM to EEPROM (the STORE operation) or from EEPROM to SRAM (the RECALL operation). In this mode SRAM functions are disabled.
STORE cycles may be initiated under user control via a software sequence or HSB assertion and are also automatically initiated when the power supply voltage level of the chip falls below VSWITCH. RECALL operations are automatically initiated upon power-up and whenever the power supply voltage level rises above VSWITCH. RECALL cycles may also be initiated by a software sequence.
address locations. By relying on READ cycles only, the STK12C68-M implements nonvolatile operation while remaining compatible with standard 8Kx8 SRAMs. During the STORE cycle, an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into the nonvolatile elements. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is critical that no other read or write accesses intervene in the sequence or the sequence will be aborted. To initiate the STORE cycle the following READ sequence must be performed:
1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0000 (hex) 1555 (hex) 0AAA (hex) 1FFF (hex) 10F0 (hex) 0F0F (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE Cycle
SRAM READ
The STK12C68-M performs a READ cycle whenever E and G are LOW and HSB and W are HIGH. The address specified on pins A0-12 determines which of the 8192 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV. If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later. The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought HIGH or W or HSB is brought LOW.
SRAM WRITE
A write cycle is performed whenever E and W are LOW and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W go HIGH at the end of the cycle. The data on pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept HIGH during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left LOW, internal circuitry will turn off the output buffers tWLQZ after W goes LOW.
Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be LOW for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation.
SOFTWARE RECALL
A RECALL cycle of the EEPROM data into the SRAM is initiated with a sequence of READ operations in a manner similar to the STORE initiation. To initiate the RECALL cycle the following sequence of READ operations must be performed:
1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0000(hex) 1555 (hex) 0AAA (hex) 1FFF (hex) 10F0 (hex) 0F0E (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL Cycle
SOFTWARE STORE
The STK12C68-M software STORE cycle is initiated by executing sequential READ cycles from six specific
Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the
4-59
STK12C68-M
EEPROM cells. The nonvolatile data can be recalled an
unlimited number of times.
AUTOMATIC RECALL
During power up, or after any low power condition (VCAP < VSWITCH), when VCAP exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated. After the initiation of this automatic RECALL, if VCAP falls below VSWITCH, then another RECALL operation will be performed whenever VCAP again rises above VSWITCH. If the STK12C68-M is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10K Ohm resistor should be connected between W and system VCC.
connected together. Each chip contains a small internal current source to pull HSB HIGH when it is not being driven low. To decrease the sensitivity of this signal to noise generated on the PC board, it may optionally be pulled to VCCX via an external resistor with a value such that the combined load of the resistor and all parallel chip connections does not exceed IHSB_OL at VOL. Do not connect this or any other pull-up to the VCAP node. If HSB is to be connected to external circuits other than other STK12C68-Ms, an external pull-up resistor should be used. During any STORE operation, regardless of how it was initiated, the STK12C68-M will continue to drive the HSB pin low, releasing it only when the STORE is complete. Upon completion of a STORE operation, the part will be disabled until HSB actually goes HIGH.
HARDWARE PROTECT
The STK12C68-M offers hardware protection against inadvertent STORE operation during low voltage conditions. When VCAP < VSWITCH, all externally initiated STORE operations will be inhibited.
AUTOMATIC STORE OPERATION
During normal operation, the STK12C68-M will draw current from VCCX to charge up a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. After power up, when the voltage on the VCAP pin drops below VSWITCH, the part will automatically disconnect the VCAP pin from VCCX and initiate a STORE operation.
HSB OPERATION
The Hardware Store Busy pin (HSB) is an open drain circuit acting as both input and output to perform two different functions. When driven low by the internal chip circuitry it indicates that a STORE operation (initiated via any means) is in progress within the chip. When driven low by external circuitry for longer than tASSERT, the chip will conditionally initiate a STORE operation after tDELAY.
READ and WRITE operations that are in progress when HSB is driven low (either by internal or external circuitry) will be allowed to complete before the STORE operation is performed, in the following manner. After HSB goes low, the part will continue normal SRAM operations for tDELAY. During tDELAY, a transition on any address or control signal will terminate SRAM operation and cause the STORE to commence. Note that if an SRAM write is attempted after HSB has been forced low, the write will not occur and the STORE operation will begin immediately.
Figure 1 shows the proper connection of capacitors for automatic store operation. The charge storage capacitor should have a capacity of at least 100F ( 20%) at 6V. Each STK12C68-M must have its own 100F capacitor. Each STK12C68-M must have a high quality, high frequency bypass capacitor of 0.1F connected between VCAP and VSS, using leads and traces that are as short as possible.
If the AutoStoreTM function is not required, then VCAP should be tied directly to the power supply and VCCX should be tied to ground. In this mode, STORE operations may be triggered through software control or the HSB pin. In either event, VCAP (Pin 1) must always have a proper bypass capacitor connected to it. In order to prevent unneeded STORE operations, automatic STOREs as well as those initiated by externally driving HSB LOW will be ignored unless at least one
Hardware-Store-Busy (HSB) is a high speed, low drive capability bi-directional control line. In order to allow a bank of STK12C68-Ms to perform synchronized STORE functions, the HSB pin from a number of chips may be
4-60
STK12C68-M
WRITE operation has taken place since the most recent STORE cycle. Note that if HSB is driven low via external circuitry and no WRITEs have taken place, the part will still be disabled until HSB is allowed to return HIGH. Software initiated STORE cycles are performed regardless of whether or not a WRITE operation has taken
place.
access cycle time is longer than 55ns. Figure 2 below shows the relationship between ICC and access times for READ cycles. All remaining inputs are assumed to cycle, and current consumption is given for all inputs at CMOS or TTL levels. Figure 3 shows the same relationship for WRITE cycles. When E is HIGH, the chip consumes only standby currents, and these plots do not apply. The cycle time used in Figure 2 corresponds to the length of time from the later of the last address transition or E going LOW to the earlier of E going HIGH or the next address transition. W is assumed to be HIGH, while the state of G does not matter. Additional current is consumed when the address lines change state while E is asserted. The cycle time used in Figure 3 corresponds to the length of time from the later of W or E going LOW to the earlier of W or E going HIGH. The overall average current drawn by the part depends on the following items: 1) CMOS or TTL input levels; 2) the time during which the chip is disabled (E HIGH); 3) the cycle time for accesses (E LOW); 4) the ratio of reads to writes; 5) the operating temperature; 6) the VCC level; and 7) output load.
PREVENTING AUTOMATIC STORES
The AutoStoreTM function can be disabled on the fly by holding HSB HIGH with a driver capable of sourcing 15mA at a VOH of at least 2.2V as it will have to overpower the internal pull-down device that drives HSB low for 50ns at the onset of an AutoStoreTM. When the STK12C68-M is connected for AutoStoreTMoperation (system VCC connected to VCCX and a 100uF capacitor on VCAP) and VCC crosses VSWITCH on the way down, the STK12C68 will attempt to pull HSB LOW ; if HSB doesn't actually get below VIL, the part will stop trying to pull HSB LOW and abort the AutoStoreTMattempt.
LOW AVERAGE ACTIVE POWER
The STK12C68-M has been designed to draw significantly less power when E is LOW (chip enabled) but the
VCAP
1
28 26
VCCX
Power Supply
100
Average Active Current (ma)
100
Average Active Current (ma)
HSB
10K Ohms (optional)
80
80
100uF 20%
+
60 40 TTL 20 CMOS 0 50 100 150 200 Cycle Time (ns)
60 40 20 0 50 100 150 200 Cycle Time (ns)
0.1uF Bypass
nvSRAM
TTL CMOS
V SS
14
Figure 1 Schematic Diagram
Figure 2 ICC (Max) Reads
Note: Typical at 25 C
Figure 3 ICC (Max) Writes
4-61
STK12C68-M
ORDERING INFORMATION
STK12C68 - 5 C 40 M Temperature Range
M = Military (-55 to 125 degrees C)
Access Time
40 = 40ns 45 = 45ns 55 = 55ns
Package
C = Ceramic 28 pin 300-mil DIP with gold lead finish K = Ceramic 28 pin 300-mil DIP with solder DIP finish L = Ceramic 28 pin LCC
Retention / Endurance
10 years / 100,000 cycles
5962-94599 01 MX X Lead Finish
A = Solder DIP lead finish C = Gold lead DIP finish X = lead finish "A" or "C" is acceptable
Package
MX = Ceramic 28 pin 300-mil DIP MY = Ceramic 28 pin LCC
Access Time
01 = 55ns 02 = 45ns
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